What is needed is an interface that will permit the synchronous transfer of data between different domains, circuits, systems or the like that are clocked at different frequencies with minimal latency and error free transfer of the data.
Transfer of data between domains clocked at different frequency ratios is possible with a circular First-In-First-Out (FIFO) buffer. However, this transfer is asynchronous creating latency in the transfer of the data which can adversely affect the speed or efficiency of performance of the domains, circuits or systems operating at different clock frequencies that need to communicate with each other. Input data from the sending domain is strobed or written into the FIFO buffer at the data rate of the sending domain with a “write pointer,” and the data is read or transferred to the receiving domain at the data rate of the receiving domain by a “read pointer.” The control logic controlling the transfer of data must be programmed to prevent the “write pointer” from overtaking the “read pointer” and vise versa. The size of the buffer and difference between the two frequency domains are important considerations for efficient and error free data transfer.